Analog Design Engineer Researcher Founder
I design analog and mixed-signal circuits — from low-jitter clocking to neuromorphic memory systems.
Circuits are arguments made in silicon — every picosecond of jitter is a claim you defend from first principles. I work across the whole stack: device physics, compact models, and the production silicon they become.
Senior Analog Design Engineer in the ATE team at Analog Devices, Colorado Springs (Feb 2026 – present). Previously two years at Texas Instruments, Seattle, designing and verifying low-jitter clocking and timing circuits for space and high-performance compute — including a PCIe Gen 6 reference clock generator and 20-output clock buffer.
M.S. in Electrical & Computer Engineering, University of Michigan, Ann Arbor — VLSI IC Design, 4.0/4.0 GPA — with graduate research on NIST- and Google-sponsored test chips for characterizing novel neuromorphic and memory devices. B.Tech in Electrical Engineering, IIT Ropar, focused on VLSI and nanomaterials. 8 publications, 67 citations, spanning RRAM/memristors, 2D-material FETs, and in-memory computing. Co-founded Shuzzly, a TBIF-incubated startup building AI/AR virtual footwear try-on.
Contact — avinashg@umich.edu · +1 734 596 9029 · Colorado Springs, CO
Performance investigation of an HfOx-based 1-transistor–1-memristor cell for implementing in-memory logic gates — my newest first-author paper, published in the IEEE Journal on Emerging and Selected Topics in Circuits and Systems, June 2026.
A browser-based tool I built for analog designers: enter a transfer function, polynomials, or a netlist, and get exact symbolic poles and zeros, Bode data, sensitivities, and inverse-design values — with live interactive plots.
Since February 2026 I design analog and mixed-signal ICs at Analog Devices, after two years building clocking and timing products at Texas Instruments in Seattle — a path from device research into production silicon.